Arithmetic, Logic, and Hierarchy

Activity A: Create a Module

We can do logic and arithmetic operations with multi-bit inputs and assign statement.

Download the zip file (lab2.zip) containing all the files required for these activities.

Create a new project in Quartus Prime and use the name tutorial2 for the top level design name. Create a SystemVerilog module with a four bit input port named SW (switches on the FPGA) and four bit input port named KEY (push buttons on the FPGA) and use the new pin assignment file soc_system.qsf.

Use the following lines to correct for the fact that the push button inputs produce a logic zero when pressed:

Logic [3:0] nKEY; 
assign nKEY = ~KEY;

This creates a four bit internal variable nKEY with the inverted values from the input port KEY. It means that the FPGA will read 0 when a key is not pressed, and 1 when a key is pressed.

Create an 8 bit output port named LEDR to handle the LEDs located on the FPGA. Test each of the following assign statements individually (one at a time) to see what each of them does:

// only one of the following lines should be active at a time, the // rest of lines of code should be commented 
assign LEDR = SW + nKEY; 
assign LEDR = SW / nKEY; 
assign LEDR = SW % nKEY; 
assign LEDR = SW & nKEY; 
assign LEDR = &SW; 

Activity B: Simulation

Create a testbench to test your module. In you testbench you can simulate the signals from the input ports SW and KEY, and observe the resulting binary value in the output port LEDR.

Activity C: Implementation

Include the files DecimalDisplayTwoDigit.sv and SevenSegmentDecoder.sv in your project.

Now add 7 bit outputs named HEX0, HEX1, HEX2, HEX3, HEX4, HEX5 to your module and connect up pairs of seven segment displays to three instances of the DecimalDisplayTwoDigit module.

Connect nKEY, SW and LEDR to these decoders. The input and output ports of the DecimalDisplayTwoDigit module are as follows:

DecimalDisplayTwoDigit 
( 
input [6:0] Value, 
output [6:0] Segments1,Segments0 
); 

Value is a 7 bits input port with the number to be displayed. Segments1, and Segments0 are 7 bits output ports that can be fed to a pair of seven segment displays to show any input in the range of 0 to 99.

Test the Activity A again and display the output from the operations using the seven segment displays from Activity C.