Skills Mapping
Dr S. Sadrafshari/Dr U Martinez-Hernandez - 15/03/2024
Schedule:
Tuesday, Week 25 .

Simulation and implementation of a full adder

Introduction

In this task, you will design a full adder using half adder modules and combinational logic. You will test your modules in simulation and program your module in the FPGA.

shows the schematic of a Full adder.

Schematic of a full adder.
Schematic of a full adder.

Design a half adder module:

shows a schematic for a half adder.

Download the zip file (adder.zip) containing all the files required.

Create a project with a module named HalfAdder with two 1-bit inputs A and B, and two 1-bit outputs Sum and Cout. Use the always_comb block for the development of this module.

Schematic of a half adder.
Schematic of a half adder.

Test your Half Adder:

Create a testbench to analyse the performance of your HalfAdder module. See the example testbench provided for this task.

Design a full adder using two half adders:

Create a new project with a module named FullAdder. The FullAdder will have three 1-bit inputs A, B and Cin, and two 1-bit outputs Sum and Cout (see ). This adder will be developed using your HalfAdder. Then, you will need to import your HalfAdder and create various instances of this modules to complete the FullAdder module.

Create a testbench for your FullAdder:

Create a testbench to analyse the performance of your FullAdder module in Questa. Your testbench will need to check that all the input combinations provide the correct Sum and Cout. Follow the example testbench provided for the half adder to create your testbench for the full adder module.

Implement you full adder on FPGA: Once you have tested your project in Questa you can create a top module in Quartus Prime to instantiate your full adder and program it into the FPGA. Test the functionality of your full adder module using the switches SW[0], SW[1] and SW[2] as input values and LEDR[0] and LEDR[1] as output values.

Citations