Simulation and synthesis of gate level logic

Activity A: Create a two gate circuit

Download the zip file (lab1.zip) containing all the files required for these activities.

Create a project by following the instructions in Sections 1 to 4 of the Getting started with SystemVerilog.

Type the following code into the top level module file. Set modulename to tutorial1 for the top level design name. Note that the module name does not have a “.sv” suffix.

module modulename 
( 
input A,B,C,D, 
output Z 
); 
wire n1; 
and(n1, A, B); 
or(Z ,n1, C, D); 
endmodule

Save the changes to this file. This code creates your top level module and instantiates (adds in) one and, one or gate that represent the following logic function:

Activity B: Simulation

Follow the instructions in Section 5 of the guide to simulate your design.

A testbench called tutorial_tb.sv has been provided for you to use. You need to make sure that the name of the testbench is the same you used for your module in Activity A. Look through the simulation waveforms and make sure that the function gives you the correct output.

Activity C: Implementation of the two gate circuit

Follow the steps in Section 6 of the guide to create an FPGA programming file.

Use the pin assignment file SimpleCombinatorial.qsf and program the FPGA as described in section 6. Use push buttons KEY0 (input A), KEY1 (input B), KEY2 (input C) and KEY3 (input D) of the FPGA board to test your design. The LEDR0 (output Z) will light up when the logic output is 1. Compare the results from the simulation and the FPGA.