Skills Mapping
Dr U. Martinez Hernandez - 09/12/2024
Skills ? :
Programming_using_a_Hardware_Description_Language
Schedule:
Week 2 .

Sequential Logic

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Introduction

In this tutorial, you will design a bi-directional shift register. The shift register should have the following specifications:

  • The shift register should be 6 bits long.
  • Clock: 1-bit input signal for the clock signal of the system.
  • LeftCtrl: 1-bit input signal. If it is set to a logic 1, the shift register should shift left on each clock cycle.
  • LeftIn: 1-bit input signal. The value of this input signal should be shifted into the shift register on each shift left clock cycle.
  • RightCtrl: 1-bit input signal. If it is set to a logic 1, the shift register should shift right on each clock cycle.
  • RightIn: 1-bit input signal. The value of this input signal should be shifted into the shift register on each shift right clock cycle.
  • Contents: 6-bit output signal with the contents of the shift register.

Activity 1 – Design a shift register

Start Quartus Prime and create a new project to develop your shift register design following the specification indicated above.

Activity 2 – Reset

Add an asynchronous reset input called AsyncReset to your module to clear the shift register Contents.

Activity 3 – Simulation

Write a testbench to check the functionality of your bi-direction shift register.

Activity 4 – Implementation in the FPGA

Add a top.sv file to your project and create an instance of your shift register to implement your bi-directional shift register in the FPGA. In the top.sv file, the input signals of your shift register should be connected to the physical ports of the FPGA as follows:

  • Connect Clock to KEY[0].
  • Connect LeftCtrl to SW[0].
  • Connect LeftIn to SW[1].
  • Connect RightCtrl to SW[9].
  • Connect RightIn to SW[8].
  • Connect Contents to LEDR[7:2].

Citations